This invention relates to a phase comparator circuit and, more particularly, to a phase comparator circuit capable of controlling phase in such a manner that a phase difference between a clock signal and a data signal takes on a prescribed value even in a case where the duty of the data signal has shifted from 100%.
In order to convert a data waveform distorted or rendered noisy by transmission to a clean digital signal in a light receiving circuit, the data signal is regenerated. At such time a clock signal is extracted from the data signal and the data signal is regenerated by a data decision circuit using the clock signal. The PLL technique is one example of means for extracting the clock signal. The PLL technique uses a phase comparator circuit, which detects the phase difference between data and a clock, and a VCO (voltage-controlled oscillator). The present invention relates to the phase comparator circuit used in this PLL arrangement.
Since a received data waveform is such that there is very little margin for decision owing to noise and distortion, it is required that the phase relationship between a data signal and clock signal input to the decision circuit be made to conform to an optimum decision point and that it not fluctuate.
FIG. 29 is a block diagram showing an example of the construction of an optical receiver in an optical communications system. The optical receiver includes a photoelectric conversion circuit 1 for converting a light signal to an electric signal, an amplifier 2 for amplifying a 10-Gbps data signal, for example, which is output by the photoelectric conversion circuit 1, an equalizer circuit 3 for equalization of the electric signal waveform, a timing extraction circuit 4 for extracting a clock signal, which has a frequency the same as that of the bit rate, from the data signal that has been equalized, and a decision circuit 5 for discriminating the data signal using the clock signal output by the timing extraction circuit 4. In an optical receiver of this kind, it is required that the phase relationship between the data signal and clock signal input to the decision circuit 5 be held at an optimum point. If this phase relationship shifts owing to a change in ambient temperature or fluctuation in power-supply voltage, discrimination can no longer be performed correctly.
Two schemes are available for the timing extraction circuit of the optical receiver that generates the clock signal. These are (1) a non-linear extraction approach using a narrow bandpass filter (see FIG. 30) and (2) a PLL technique (see FIG. 32) using a phase comparator circuit and a VCO.
FIG. 30 is a block diagram showing the construction of a timing extraction circuit using non-linear extraction. This arrangement includes a non-linear extraction circuit 110 for sensing rising and falling edges of an entered data signal, a narrow bandpass filter 111 having a center frequency the same as the bit rate of the data, and a limiter amplifier 112, which is a narrow-band amplifier. The non-linear circuit 110 has a branching circuit 110a for branching the data signal in two directions, a delay circuit 110b for delaying, by a prescribed length of time (one-half of the time that corresponds to one bit), one of the branched data signals, and an EX-OR (exclusive-OR) circuit 110c for taking the exclusive-OR between the data signal and the output signal of the delay circuit to generate an edge signal having pulses at the rising and falling edges of the data signal. FIG. 31 is a waveform diagram illustrating operation of this circuitry. The EX-OR circuit 100c senses the rising and falling edges of the data signal to generate pulses P1, the bandpass filter 111 extracts the clock component, which has a frequency identical with that of the data bit rate, from the output of the EX-OR circuit, and the limiter amplifier 112 amplifies the clock component to a fixed amplitude.
With the non-linear extraction method, a SAW filter or dielectric filter is used as the narrow bandpass filter 111. However, problems of size arise in regard to designing integrated circuits or the like, and it is difficult to reduce the size of the optical transceiver module.
Although the limiter amplifier 112 is used as means for dealing with the fact that the extracted clock component is small, that it is necessary to compensate for filtering loss and that it is required to suppress a fluctuation in the amplitude of the clock with respect to a change in the pattern of the data signal, a problem is that the fluctuation in the phase of this circuit is large.
In comparison with the non-linear extraction scheme, the PLL scheme makes it possible to incorporate almost all of the circuitry, inclusive of the VCO, on an IC chip, as a result of which the device can be made very small. In addition, even if a fluctuation in phase arises, this fluctuation is sensed by the phase comparator circuit and therefore the fluctuation in phase is compensated for by the PLL. FIG. 32 is a basic block diagram of a timing extraction circuit that employs a PLL. Numeral 4 denotes the timing extraction circuit and numeral 5 the decision circuit. The timing extraction circuit 4 includes a phase comparator circuit 121 for comparing the phases of a data signal DATA and clock signal CLK, a loop filter 122 for smoothing a voltage signal that conforms to a phase-difference signal output by the phase comparator circuit 121, and a VCO circuit 123 for generating the clock signal CLK having a frequency conforming to the output of the loop filter 122. A variety of phase comparator circuits that sense the phase difference between data and clock signals have been devised. FIG. 33 illustrates the basic portion of a phase comparator circuit that uses a D-type flip-flop (D-FF) 131 and an EX-OR circuit 132 (see IEEE Transactions on Electron Devices VOL. ED-32, No. 12 December 1985 “A Self-Correcting Clock Recovery Circuit”, Hogge, pp. 2704–2706). FIG. 34 is a timechart associated with this circuit.
The flip-flop 131 outputs a data discrimination signal DTRN, which indicates the level of the data signal DATA at the moment the clock signal CLK rises. More specifically, the flip-flop 131 stores and outputs the level (“1” or “0”) of the data signal DATA, which is input to the data input terminal (the D terminal), at a rising edge of the clock signal CLK input to the clock input terminal (the C terminal) and holds this level until the next rising edge of the clock signal. The EX-OR circuit 132 outputs the exclusive-OR data of the data signal DATA and the data discrimination signal DTRN output by the flip-flop 131 and outputs the result as a phase-difference signal PHASE indicative of the phase difference between the data signal and the clock signal.
It will be understood from FIG. 34 that the width of the output pulse PHASE from EX-OR circuit 132 is decided by a delay time extending from the rising or falling edge of the data signal DATA to the following rising edge of the clock signal CLK. Consequently, the average value of the signal PHASE takes on a value that conforms to the phase difference between the data signal DATA and the clock signal CLK. Let “0” and “1” represent the low and high levels, respectively, of the output signal PHASE of the EX-OR circuit 132. If the input data is random and the mark rate which is rate of “1” is ½, the phase comparison characteristic of the phase comparator circuit becomes a sawtooth waveform characteristic with respect to phase θ when the average value of the phase difference signal PHASE is between 0 and 0.5.
In order to make the phase of the data signal DATA and clock signal CLK equal to a prescribed value φ, the PLL-type timing extraction circuit 4 (FIG. 32) performs control in such a manner that the output of the phase comparator circuit 121 will be rendered constant (=S). In order for the PLL to stabilize at the phase φ, control is carried out to advance the phase of the clock signal, i.e., to raise the frequency of the VCO circuit 123, if the phase of the clock signal is greater than φ with respect to the data signal (if the phase thereof is lagging). Control is carried out to retard the phase of the clock signal, i.e., to lower the frequency of the VCO circuit 123, if the phase of the clock signal is less than φ with respect to the data signal (if the phase thereof is leading). More specifically, if the PLL is constructed using the phase comparator circuit 121 having the phase comparator characteristic of FIG. 35 so as to raise the frequency of the VCO circuit 123 when the average value of the phase-difference signal is larger than the set level S (when phase is lagging) and so as to lower the frequency of the VCO circuit 123 when the average value of the phase-difference signal is less than the set level S (when phase is leading), then the phase difference between the data signal and the clock signal can be set to any phase φ of between 0 and 2π.
If the duty of the data signal shifts from 100% in the conventional phase comparator circuit, there are instances where the PLL is locked to a different phase. The duty referred to here is the ratio between the duration T1 of data “1” and T, where f (=1/T) is the bit rate.
If in regard to phases of 0 to 2π in one period the phase comparison characteristic of the phase comparator circuit has a plurality of slopes in the same direction with respect to a change in phase and a plurality of phases for which the average values are identical exist, then it is possible that the PLL will lock with respect to any of these plurality of phases, making it impossible to determine the phase.
If the duty is 100%, only one slope in the same direction will exist in one period, as illustrated in FIG. 35. The foregoing problem does not arise, therefore, because there is only one phase for which the average value takes on the same value. If the duty shifts from 100%, however, two slopes of the same direction will exist is one period and phases for which the average values are the same will exist. This gives rise to the problem mentioned above.
FIG. 36 is a timing chart for a case where the duty is 75%. This illustrates a change in the duty brought about by advancing the phase of the falling edge of the data signal DATA (a). For the sake of comparison, the waveform for the case where the duty is 100% is indicated by the dashed line. As long as the phase difference between the data signal DATA (a) and the clock signal CLK (b) is small, the pulse width of the phase-difference signal PHASE (d) merely differs from that of this pulse when the duty is 100%. However, if the phase difference between the data signal DATA (a) and a clock signal CLK (b′) exceeds 1.5π (75% of one period), the pulse that was produced by the falling edge of the data signal vanishes. As a consequence, the sawtooth phase comparison characteristic has two stages in one period (=2π), as indicated by the solid line in FIG. 37. If, in order to set the phase difference between the data and clock to φ1, control is performed in such a manner that the average value of the phase-difference signal becomes V1, there is a possibility that the PLL will synchronize at the phase of φ2 in addition to the phase of φ1 and, hence, it will no longer be possible to determine the phase. In general, the phase difference at which the phase comparison characteristic becomes discontinuous is 2π·(d/100), where d(%) represents the duty.
The foregoing is for a case where the duty falls below 100%. If the duty exceeds 100%, the sawtooth phase comparison characteristic becomes as shown by the solid line in FIG. 38, where it is seen that the characteristic takes on two stages in one period (=2π) in this instance as well. FIG. 38 is for a case where the duty is 125%. Here the phase difference at which the phase comparison characteristic becomes discontinuous is 2π·(d/100), where the duty is represented by (100+d)(%). If the duty is 125%, the point of discontinuity is π/2.